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1/66 ? semiconductor msm54v25632a description the msm54v25632a is a synchronous graphics random access memory organized as 128 k words 32 bits 2 banks. this device can operate up to 100 mhz by using synchronous interface. in addition, it has 8-column block write function and write per bit function which improves performance in graphics systems. features ? 131,072 words 32 bits 2 banks memory ? single 3.3 v 0.3 v power supply ? lvttl compatible inputs and outputs ? all input signals are latched at rising edge of system clock ? auto precharge and controlled precharge ? internal pipelined operation: column address can be changed every clock cycle ? dual internal banks controlled by a9 (bank address: ba) ? independent byte operation via dqm0 to dqm3 ? 8-column block write function ? persistent write per bit function ? programmable burst sequence (sequential/interleave) ? programmable burst length (1, 2, 4, 8 and full page) ? programmable cas latency (1, 2 and 3) ? burst stop function (full-page burst) ? power down operation and clock suspend operation ? auto refresh and self refresh capability ? 1,024 refresh cycles/16 ms ? package: 100-pin plastic qfp (qfp100-p-1420-0.65-bk4) (product : msm54v25632a-xxagbk4) xx indicates speed rank. product family ? semiconductor msm54v25632a 131,072-word 32-bit 2-bank synchronous graphics ram msm54v25632a-10 family msm54v25632a-12 100-pin plastic qfp (14 20 mm) 100 clock frequency mhz (max.) 83 package e2l0068-19-61 this version: jun. 1999 previous version: sep. 1998
2/66 ? semiconductor msm54v25632a pin configuration (top view) dq3 100-pin plastic qfp 1 v cc q 2 dq4 3 dq5 4 v ss q 5 dq6 6 dq7 7 v cc q 8 dq16 9 dq17 10 v ss q 11 dq18 12 dq19 13 v cc q 14 v cc 15 v ss 16 dq20 17 dq21 18 v ss q 19 dq22 20 dq23 21 v cc q 22 dqm0 23 dqm2 24 we 25 cas 26 ras 27 cs 28 ba (a9) 29 nc 30 dq28 v cc q dq27 dq26 v ss q dq25 dq24 v cc q dq15 dq14 v ss q dq13 dq12 v cc q v ss v cc dq11 dq10 v ss q dq9 dq8 v cc q nc dqm3 dqm1 clk cke dsf nc a8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a0 31 a1 32 a2 33 a3 34 v cc 35 nc 36 nc 37 nc 38 nc 39 nc 40 nc 41 nc 42 nc 43 nc 44 nc 45 v ss 46 a4 47 a5 48 a6 49 a7 50 dq2 v ss q dq1 dq0 v cc nc nc nc nc nc nc nc nc nc nc v ss dq31 dq30 v ss q dq29 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 pin name function pin name function a0 - a9 address inputs dqm0 - dqm3 dq mask enable a0 - a8 row address inputs dsf special function enable a0 - a7 column address inputs cke clock enable a9 bank address clk system clock input dq0 - dq31 data inputs/outputs v cc supply voltage cs chip select v ss ground ras row address strobe v cc q supply voltage for dq cas column address strobe v ss q ground for dq we write enable nc no connection note: the same power supply voltage must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin.
3/66 ? semiconductor msm54v25632a block diagram a0 dq0 to 31 dqm0 to 3 32 32 32 a1 a2 a9 address buffers column decoders sense amplifiers 4mb memory cells bank - a row decoders column decoders sense amplifiers 4mb memory cells bank - b refresh counter i/o buffers color register (32 bits) mask register (32 bits) row decoders clk cke cs ras cas we dsf v cc v ss timing generator
4/66 ? semiconductor msm54v25632a pin description * notes: 1. when cs is set "high" at a clock transition from "low" to "high", all inputs except clk, cke, dqm0, dqm1, dqm2, and dqm3 are invalid. 2. when issuing an active, read or write command, the bank is selected by a9. 3. the auto precharge function is enabled or disabled by the a8 input when the read or write command is issued. a9 0 1 active, read or write bank a bank b a8 0 operation after the end of burst, bank a holds the active status. a9 0 0 0 after the end of burst, bank b holds the active status. 1 1 after the end of burst, bank a is precharged automatically. after the end of burst, bank b is precharged automatically. 1 1 4. when issuing a precharge command, the bank to be precharged is selected by the a8 and a9 inputs. a8 0 0 1 a9 0 1 x operation bank a is precharged. bank b is precharged. both banks a and b are precharged. clk fetches all inputs at the "h" edge. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be masked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. row & column multiplexed. row address: ra0 C ra8 column address: ca0 C ca7 ras cas we functionality depends on the combination. for details, see the function truth table. dqm0 - dqm3 masks the read data of two clocks later when dqm0 - dqm3 are set "h" at the "h" edge of the clock signal. masks the write data of the same clock when dqm0 - dqm3 are set "h" at the "h" edge of the clock signal. address dqi data inputs/outputs are multiplexed on the same pin. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, dqm0, dqm1, dqm2 and dqm3. selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. a9 = "l" : bank a, a9 = "h" : bank b ba (a9) dsf dsf is part of the inputs of graphics command of the msm54v25632a. if dsf is inactive (low level), msm54v25632a operates just like sdram.
5/66 ? semiconductor msm54v25632a command operation mode register set command ( cs , ras , cas , we , dsf = "low") the msm54v25632a has the mode register that defines the operation mode " cas latency, burst length, burst sequence". the mode register is composed of ten bits of memories corresponding to address inputs a0 - a8 and ba. the mode register set command should be executed just after the msm54v25632a is powered on. before entering this command, all banks must be precharged. next command can be issued after t rsc . special mode register set command ( cs , ras , cas , we = "low", dsf = "high") the msm54v25632a has the 32-bit color register for block write operation and the 32-bit mask register for write per bit operation. the special mode register set command performs loading mask register or color register. when a5 is "high", the mask data presented on the dq0 - dq31 is latched into the mask register. when a6 is "high", the color data presented on the dq0 - dq31 is latched into the color register. the special mode register set command must be executed before masked block write and write per bit operations. next command can be issued after t rsc . auto refresh command ( cs , ras , cas , dsf = "low", we , cke = "high") the auto refresh command performs refresh automatically by the address counter. the refresh operation must be performed 1024 times within 16 ms and the next command can be issued after t rc from last auto refresh command. before entering this command, all banks must be precharged. self refresh entry/exit command ( cs , ras , cas , dsf, cke = "low", we = "high") the self refresh operation continues after the self refresh entry command is entered, with cke level left "low". this operation terminates by making cke level "high". the self refresh operation is performed automatically by the internal address counter on the msm54v25632a chip. in self refresh mode, no external refresh control is required. before entering self refresh mode, all banks must be precharged. next command can be issued after t rc . single bank precharge command ( cs , ras , we , dsf, a8 = "low", cas = "high") the single bank precharge command triggers bank precharge operation. precharge bank is selected by ba. all banks precharge command ( cs , ras , we , dsf = "low", cas , a8 = "high") the all bank precharge command triggers precharge of both bank a and bank b.
6/66 ? semiconductor msm54v25632a bank active and masked write disable command ( cs , ras , dsf = "low", cas , we = "high") the bank active command activates the bank selected by ba. the bank active command corresponds to conventional dram's ras falling operation. row addresses "a0 - a8 and ba" are strobed. after this command, the write command and block write command for that bank works as the no write per bit operation. bank active and masked write enable command ( cs , ras = "low", cas , we , dsf = "high") the bank active command activates the bank selected by ba. the bank active command corresponds to conventional dram's ras falling operation. row addresses "a0 - a8 and ba" are strobed. after this command, the write command and block write command for that bank works as the write per bit operation. write command ( cs , cas , we , dsf, a8 = "low", ras = "high") the write command is required to begin burst write operation. then burst access initial bit column address is strobed. write with auto precharge command ( cs , cas , we , dsf = "low", ras , a8 = "high") the write with auto precharge command is required to begin burst write operation with automatic precharge after the burst write. any command that interrupts this operation cannot be issued. masked block write command ( cs , cas , we , a8 = "low", ras , dsf = "high") the masked block write command is required to begin block write operation with column mask. the masked block write operation performs writing in the 8 memory cells selected by column addresses "a3 - a7". in this operation, data in color register is written to memory cells with the column mask functions. at the same time, this command can perform write per bit operation. the block write operation is not bursted.
7/66 ? semiconductor msm54v25632a 1 dq0 8 column 8 dq note : location "*" can not be loaded. color register i/o mask column mask 11001110 11111010 10010011 1 * * 1 * * 1 1 1 * * 1 * * 1 0 0 * * 0 * * 0 0 0 * * 0 * * 0 1 1 * * 1 * * 1 * * * * * * * * 1 1 * * 1 * * 1 * * * * * * * * column 7 column 6 column 5 column 4 column 3 column 2 column 1 column 0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 remark: 1. this diagram shows only for dq0 - 7. the other dq is similar as this. column mask dq0 - 7 : column mask for dq0 - 7 dq8 - 15 : column mask for dq8 - 15 dq16 - 23: column mask for dq16 - 23 dq24 - 31: column mask for dq24 - 31 write per bit mask data = mask register + dqmi dqmi is prior to data of mask register. block write function
8/66 ? semiconductor msm54v25632a masked block write with auto precharge command ( cs , cas , we = "low", ras , dsf, a8 = "high") the masked block write with auto precharge command performs precharging at the bank selected by ba automatically after masked block write. read command ( cs , cas , dsf, a8 = "low", ras , we = "high") the read command is required to begin burst read operation. then burst access initial bit column address is strobed. read with auto prechaege command ( cs , cas , dsf = "low", ras , we , a8 = "high") the read with auto precharge command is required to begin burst read operation with auto precharge after the burst read. any command that interrupts this operation cannot be issued. no operation command ( cs , dsf = "low", ras , cas , we = "high") the no operation command does not trigger any operation. device deselect command ( cs = "high") the device deselect command disables the ras , cas , we , dsf and address input. this command does not trigger any operation. data write/output enable command (dqmi = "low") the data write/output enable command enables dq0 - dq31 in read or write. the each dqm0, 1, 2 and 3 corresponds to dq0 - dq7, dq8 - dq15, dq16 - dq23 and dq24 - dq31 respectively. data mask/output disable command (dqmi = "high") the data mask/output disable command disables dq0 - dq31. in read cycle output buffers are disabled after 2 clocks . in write cycle input buffers are disabled at the same clock. the each dqm0, 1, 2 and 3 corresponds to dq0 - dq7, dq8 - dq15, dq16 - dq23 and dq24 - dq31 respectively. burst stop command ( cs , we , dsf = "low", ras , cas = "high") the burst stop command stops burst access when the access is in full page. after the burst stop command is entered, the output buffer goes into high impedance state.
9/66 ? semiconductor msm54v25632a truth table command truth table dqm truth table function dqmi data write/output enable l data mask/output disable h function cs ras cas we dsf address a9 a8 a7 - a0 device deselect h no operation l h h h l burst stop in full page l h h l l read l h l h l ba l ca read with auto precharge l h l h l ba h ca write l h l l l ba l ca write with auto precharge l h l l l ba h ca masked block write l h l l h ba l ca masked block write with auto precharge lhl lhbahca bank activate l l h h l ba ra bank activate with wpb enable l l h h h ba ra precharge select bank l l h l l ba l precharge all banks l l h l l h mode register set l l l l l op. code special register set l l l l h op. code
10/66 ? semiconductor msm54v25632a function truth table (1/5) current state cs ras cas we dsf address note action idle h nop or power down lhhh nop or power down lhhlh illegal lhhll 2 illegal lhlhh illegal l h l h l ba, ca, a8 2 illegal l h l l h ba, ca, a8 2 illegal l h l l l ba, ca, a8 2 illegal l l h h h ba, ra row active with wpb l l h h l ba, ra row active llhlh illegal l l h l l ba, a8 3 nop lllhh illegal lllhl 4 auto refresh/self refresh l l l l h op-code special register write l l l l l op-code mode register write row active (act) h nop lhhh nop lhhlh illegal lhhll 2 illegal lhlhh illegal l h l h l ba, ca, a8 read l h l l h ba, ca, a8 block write l h l l l ba, ca, a8 write l l h h h ba, ra 2 illegal l l h h l ba, ra 2 illegal llhlh illegal l l h l l ba, a8 precharge lllhh illegal lllhl illegal l l l l h op-code special register write l l l l l op-code illegal note 1 2
11/66 ? semiconductor msm54v25632a current state cs ras cas we dsf address note action read (rd) h nop (continue row active after burst ends) lhhh nop (continue row active after burst ends) lhhlh illegal lhhll 1, 2, 4, 8 burst length; illegal full page burst; burst stop ? bank active lhlhh illegal l h l h l ba, ca, a8 term burst, new read l h l l h ba, ca, a8 term burst, start block write l h l l l ba, ca, a8 term burst, start write l l h h h ba, ra illegal l l h h l ba, ra illegal llhlh illegal l l h l l ba, a8 term burst, execute row precharge lllhh illegal lllhl illegal l l l l h op-code illegal l l l l l op-code illegal nop (continue row active after burst ends) nop (continue row active after burst ends) illegal 1, 2, 4, 8 burst length; illegal full page burst; burst stop ? row active illegal term burst, start read term burst, new block write term burst, new write illegal illegal illegal term burst, execute row precharge illegal illegal illegal illegal write/block write (wt/bw) h lhhh lhhlh lhhll lhlhh l h l h l ba, ca, a8 l h l l h ba, ca, a8 l h l l l ba, ca, a8 l l h h h ba, ra 2 l l h h l ba, ra 2 llhlh l l h l l ba, a8 lllhh lllhl l l l l h op-code l l l l l op-code note 1 2 2 function truth table (2/5)
12/66 ? semiconductor msm54v25632a current state cs ras cas we dsf address note action read with auto precharge (rap) h lhhh lhhlh lhhll lhlhh l h l h l ba, ca, a8 l h l l h ba, ca, a8 l h l l l ba, ca, a8 l l h h h ba, ra 2 l l h h l ba, ra 2 llhlh l l h l l ba, a8 2 lllhh lllhl l l l l h op- code l l l l l op- code note 1 nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal write/block write with auto precharge (wap/bwap) h lhhh lhhlh lhhll lhlhh l h l h l ba, ca, a8 l h l l h ba, ca, a8 l h l l l ba, ca, a8 l l h h h ba, ra 2 l l h h l ba, ra 2 llhlh l l h l l ba, a8 2 lllhh lllhl l l l l h op- code l l l l l op- code nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal function truth table (3/5)
13/66 ? semiconductor msm54v25632a current state cs ras cas we dsf address note action precharging (pre) h 2 2 2 2 2 2 3 nop ? idle after t rp lhhh nop ? idle after t rp lhhlh illegal lhhll illegal lhlhh illegal l h l h l ba, ca, a8 illegal l h l l h ba, ca, a8 illegal l h l l l ba, ca, a8 illegal illegal illegal illegal nop ? idle after t rp illegal illegal special register write illegal l l h h h ba, ra l l h h l ba, ra llhlh l l h l l ba, a8 lllhh lllhl l l l l h op-code l l l l l op-code note 1 refreshing (ref) h nop ? idle after t rc lhhh nop ? idle after t rc lhhlh illegal lhhll illegal lhlhh illegal illegal illegal illegal l h l h l ba, ca, a8 l h l l h ba, ca, a8 l h l l l ba, ca, a8 illegal illegal illegal illegal illegal illegal illegal illegal l l h h h ba, ra l l h h l ba, ra llhlh l l h l l ba, a8 lllhh lllhl l l l l h op-code l l l l l op-code function truth table (4/5)
14/66 ? semiconductor msm54v25632a current state cs ras cas we dsf address note action nop nop illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal illegal mode register access (mra) h lhhh lhhlh lhhll lhlhh l h l h l ba, ca, a8 l h l l h ba, ca, a8 l h l l l ba, ca, a8 l l h h h ba, ra l l h h l ba, ra llhlh l l h l l ba, a8 lllhh lllhl l l l l h op-code l l l l l op-code note 1 special mode register access (smra) h nop lhhh nop lhhlh illegal lhhll illegal lhlhh illegal illegal illegal illegal l h l h l ba, ca, a8 l h l l h ba, ca, a8 l h l l l ba, ca, a8 illegal illegal illegal illegal illegal illegal illegal illegal l l h h h ba, ra l l h h l ba, ra llhlh l l h l l ba, a8 lllhh lllhl l l l l h op-code l l l l l op-code function truth table (5/5) notes: 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. nop to bank precharging or in idle state. precharges activated bank by ba or a8. 4. illegal if any bank is not idle. abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge = high or low level (don't care)
15/66 ? semiconductor msm54v25632a function truth table for cke current state (n) cken-1 address h lh l lhhh llhhl llhl lll l h lh l lhhh llhhl llhl lll l h hh h lhhh hlhhl hlhl hllhl hlllh h h l l self refresh (sref) power down (pd) all banks idle any state other action invalid exit self refresh ? abi exit self refresh ? abi illegal illegal illegal nop (maintain self refresh) invalid exit power down ? abi exit power down ? abi illegal illegal illegal nop (continue power down mode) refer to table enter power down enter power down illegal illegal illegal enter self refresh refer to operations in table begin clock suspend next cycle enable clock of next cycle continue clock suspension cken h h h h h l h h h h h l h l l l l l l h l h l (abi) than listed above h llll illegal l l nop l l note 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 cs ras cas we dsf notes: 5. if the minimum set-up time t pde is satisfied when cke transitions from "l" to "h", cke operates asynchronously so that a command can be input in the same internal clock cycle. 6. power-down and self refresh can be entered only when all the banks are in an idle state.
16/66 ? semiconductor msm54v25632a mode set address keys special mode set address keys a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 cas latency (cl) burst type (bt) burst length (bl) tm a7 a8 mode setting 0 0 reserved 1 0 reserved 0 1 burst 0 single bit 1 length a9 operation code write burst length 000 reserved 0 sequential 000 1 1 001 1 interleave 001 2 2 010 010 4 4 011 011 8 8 1 2 3 100 reserved 100 reserved reserved 101 reserved 101 reserved reserved 110 reserved 110 reserved reserved 111 reserved 111 full page reserved reserved 1 1 note : if lc and lm are both high (1), data of mask and color register will be unknown. power on sequence 1. with cke = "h", dqm = "h" and the other inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 m s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply an auto-refresh eight or more times. 5. enter the mode register setting command. 0 a9 0 a8 0 a7 lc a6 lm a5 0 a4 0 a3 0 a2 0 a1 0 a0 a6 load color (lc) function a5 load mask (lm) function disable disable enable enable 00 11
17/66 ? semiconductor msm54v25632a burst length and sequence bl = 2 starting address sequential type interleave type (column address a0, binary) 0 0, 1 not supported 1 1, 0 not supported bl = 4 starting address sequential type interleave type (column address a1 - a0, binary) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 bl = 8 starting address sequential type interleave type (column address a2 - a0, binary) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4 ,5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 bl = full : sequential only
18/66 ? semiconductor msm54v25632a precharge read interrupted by precharge cl = 1 : at the same clock as the last read data. cl = 2 or 3 : one clock earlier than the last read data. 012345678 bl = 4 (t ras is satisfied) hi-z clk dq cl = 1 q2 q3 q4 rd pre hi-z dq cl = 2 rd pre dq cl = 3 rd pre hi-z q1 q2 q3 q4 q1 q2 q3 q4 q1
19/66 ? semiconductor msm54v25632a auto precharge read with auto precharge 012345678 bl = 4 (t ras is satisfied) hi-z clk dq cl = 1 q2 q3 q4 rap hi-z dq cl = 2 rap dq cl = 3 rap hi-z auto precharge starts auto precharge starts auto precharge starts q1 q2 q3 q4 q1 q2 q3 q4 q1
20/66 ? semiconductor msm54v25632a write with auto precharge 012345678 bl = 4 (t ras is satisfied) hi-z clk dq cl = 1 wap hi-z dq cl = 2 wap dq cl = 3 wap hi-z auto precharge starts auto precharge starts auto precharge starts d2 d3 d4 d1 d2 d3 d4 d1 d2 d3 d4 d1 block write with auto precharge 012345 (t ras is satisfied) hi-z clk dq cl = 1 bwap hi-z dq cl = 2 db bwap dq cl = 3 bwap hi-z auto precharge starts auto precharge starts auto precharge starts t bwc db db
21/66 ? semiconductor msm54v25632a read/write command interval read to read command interval 012345678 bl = 4, cl = 2 hi-z clk dq qb1 qb2 qb3 qb4 rd-a rd-b qa1 1 cycle write to write command interval 012345678 bl = 4, cl = 2 hi-z clk dq db1 db2 db3 db4 wt-a wt-b da1 1 cycle
22/66 ? semiconductor msm54v25632a write to read command interval 012345678 bl = 4 hi-z clk dq cl = 1 qb2 qb3 qb4 wt-a rd-b dq cl = 2 dq cl = 3 qb1 da1 1 cycle hi-z qb2 qb3 qb4 wt-a rd-b qb1 da1 hi-z qb2 qb3 qb4 wt-a rd-b qb1 da1
23/66 ? semiconductor msm54v25632a block write to write/block write command interval block write to read command interval 012345678 hi-z clk dq bw-a db da bw-b cl = 2 t bwc dq bw-a db1 db2 db3 db4 da wt-b bl = 4, cl = 2 t bwc 012345678 hi-z clk dq cl = 1 bw-a dq cl = 2 dq cl = 3 qb2 qb3 qb4 qb1 da rd-b t bwc hi-z bw-a qb2 qb3 qb4 qb1 da rd-b t bwc hi-z bw-a qb2 qb3 qb4 qb1 da rd-b t bwc
24/66 ? semiconductor msm54v25632a read to write/block write command interval 012345678 cl = 1, 2, 3 hi-z clk dqm rd-a wt-b dq db2 db3 db4 db1 1 cycle bl = 8, cl = 1, 2 012345678 9 clk dqm cl = 1 rd-a wt-b dq qa2 qa3 qa4 qa1 db2 db3 db1 hi-z is necessary dqm cl = 2 rd-a wt-b dq qa1 qa2 qa3 db2 db3 db1 hi-z is necessary
25/66 ? semiconductor msm54v25632a 012345678 ex.) cl = 3, bl = 4 clk dqm rd-a wt-b dq qa1 db2 db3 db1 hi-z is necessary ex.) cl = 1, bl = 4 clk dqm wt-a rd-b dq da1 qb2 qb3 hi-z da2 da3 | 0123456789 qb4 note note : dqm can mask both data-in and data-out in this s p ecial case.
26/66 ? semiconductor msm54v25632a burst termination burst stop command in full page 012345678 bl = full page, cl = 1, 2, 3 hi-z clk d2 d3 d4 wt bst cl = 1, 2, 3 dq d1 01234 5678 bl = full page, cl = 1, 2, 3 hi-z clk q2 q3 rd bst cl = 1 dq q1 hi-z q2 q3 cl = 2 dq q1 hi-z q2 q3 cl = 3 dq q1
27/66 ? semiconductor msm54v25632a precharge termination in read cycle 012345678 bl = x, cl = 1 clk rd pre act dq q1 q3 q4 q2 hi-z t rp 012345678 bl = x, cl = 2 clk rd pre act dq q1 q3 q4 q2 hi-z t rp 012345678 bl = x, cl = 3 clk rd pre act dq q1 q3 q2 hi-z t rp
28/66 ? semiconductor msm54v25632a precharge termination in write cycle 012345678 bl = x, cl = 1, 2 clk wt pre act dq d3 d2 d1 d4 hi-z t rp d5 note : d5 data will not be written 012345678 bl = x, cl = 3 clk wt pre act dq d3 d2 d1 hi-z t rp d4 d5 note : d5 data will not be written
29/66 ? semiconductor msm54v25632a electrical characteristics note : all voltages are referenced to v ss . absolute maximum ratings parameter unit symbol voltage on power supply pin relative to gnd v cc , v cc qv voltage on input pin relative to gnd v t v short circuit output current i os ma power dissipation p d w storage temperature t stg c condition ta = 25c rating C1.0 to 4.6 C1.0 to v cc + 0.5 4.6 50 1 operating temperature t opr c 0 to 70 C55 to 150 caution: exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter min. symbol power supply voltage v cc 3.0 input high voltage v ih 2.0 input low voltage v il C0.3 typ. 3.3 max. 3.6 v cc + 0.3 0.8 unit v v v (ta = 0c to 70c) capacitance parameter min. symbol input capacitance (clk, cke, cs , ras , cas , we , dsf, dqm) c i1 c i2 input/output capacitance (dq0 - dq31) c i/o max. 6 6 7 unit pf pf pf (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) input capacitance (a0 - a9) dc characteristics 1 parameter symbol test condition i oh = C2 ma output high voltage v oh unit v max. min. 2.4 i ol = 2 ma output low voltage v ol v 0.4 0 v v i 3.6 v; all other pins not under test = 0 v input leakage current i li m a 10 C10 d out is disabled, 0 v v o 3.6 v output leakage current i lo m a 10 C10
30/66 ? semiconductor msm54v25632a dc characteristics 2 notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck (min.) . 2. i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck (min.) . parameter symbol test condition burst length = 1, t ras 3 t ras (min.) , t rp 3 t rp (min.) , i o = 0 ma operating current i cc1 unit max. note 155 175 ma 1 cke v il (max.), t ck = 15 ns precharge standby current i cc2 p ma 4 cke v il (max.) , t ck = in power down mode i cc2 ps 3 cke 3 v ih (min.) , t ck = 15 ns, precharge standby current cs 3 v ih (min.) , in non power down mode i cc2 n 60 input signals are changed one time during 30 ns. ma cke 3 v ih (min.) , t ck = , i cc2 ns 30 input signals are stable. cke v il (max.) , t ck = 15 ns active standby current i cc3 p ma 4 cke v il (max.) , t ck = in power down mode i cc3 ps 3 cke 3 v ih (min.) , t ck = 15 ns, active standby current cs 3 v ih (min.) , in non power down mode i cc3 n 70 input signals are changed one time during 30 ns. ma cke 3 v ih (min.) , t ck = , i cc3 ns 35 input signals are stable. t ck 3 t ck (min.) , operating current i cc4 120 130 i o = 0 ma (burst mode) 180 240 170 ma 2 230 t rc 3 t rc (min.) refresh current i cc5 cke 0.2 v self refresh current i cc6 ma 3 t ck 3 t ck (min.) , i o = 0 ma, operating current cas cycle = 20 ns (block write mode) i cc7 ma 240 cas latency = 1 cas latency = 2 cas latency = 3 -12 -10 4 3 60 30 4 3 70 35 3 240 165 145 ma 3 max.
31/66 ? semiconductor msm54v25632a ac characteristics test conditions ? ac measurements assume t t = 1 ns. ? reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . ? if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih (min.) and v il (max) . ? an access time is measured at 1.4 v. 2.8 v t ck 1.4 v clk v ss 2.8 v 1.4 v input v ss t ch t cl t setup t hold output 1.4 v 1.4 v t oh t ac
32/66 ? semiconductor msm54v25632a synchronous characteristics parameter unit note msm54v25632a -10 cas latency = 3 t ck3 min. 10 max. (100 mhz) ns symbol min. 12 max. (83 mhz) clock cycle time cas latency = 2 t ck2 15 (66 mhz) ns 18 (55 mhz) cas latency = 1 t ck1 30 (33 mhz) ns 36 (28 mhz) cas latency = 3 t ac3 9 ns 1 10 access time from clk cas latency = 2 t ac2 13 ns1 15 cas latency = 1 t ac1 27 ns1 32 8 12 26 clk high level width t ch 3.5 ns 4 clk low level width t cl 3.5 ns 4 data-out hold time t oh 3 ns 3 data-out low-impedance time t lz 0 ns 0 data-out cas latency = 3 t hz3 38 ns 3 high-impedance time cas latency = 2 t hz2 312 ns 3 cas latency = 1 t hz1 326 ns 3 data-in setup time t ds 3 ns 3.5 data-in hold time t dh 1 ns 1.5 address setup time t as 3 ns 3.5 address hold time t ah 1 ns 1.5 cke setup time t cks 3 ns 3.5 cke hold time t ckh 1 ns 1.5 msm54v25632a -12 t cms 3 ns 3.5 command ( cs , ras , cas , we , dsf, dqm) setup time t cmh 1 ns 1.5 command ( cs , ras , cas , we , dsf, dqm) hold time note 1. output load. output z = 50 w 30 pf 50 w 1.4 v
33/66 ? semiconductor msm54v25632a asynchronous characteristics msm54v25632a -12 parameter unit note msm54v25632a -10 t rc min. 90 max. ns symbol min. 108 ref to ref/act command period t ras 60 120,000 ns 72 120,000 act to pre command period t rp 30 ns 36 pre to act command period t rcd 30 ns 36 delay time act to read/write command t rrd 20 ns 24 act (0) to act (1) command period cas latency = 3 t dpl3 20 ns 24 data-in to pre cas latency = 2 t dpl2 20 ns 24 command period cas latency = 1 t dpl1 20 ns 24 cas latency = 3 t dal3 5 clk 5 data-in to act (ref) cas latency = 2 t dal2 3 clk 3 command period cas latency = 1 t dal1 2 clk 2 (auto precharge) t bwc 20 ns 24 block write cycle time cas latency = 3 t bpl3 30 ns 36 block write data-in cas latency = 2 t bpl2 30 ns 36 to pre command cas latency = 1 t bpl1 30 ns 36 period cas latency = 3 t bal3 6 clk 6 block write data-in active (ref) command period (auto precharge) cas latency = 2 t bal2 4 clk 4 cas latency = 1 t bal1 2 clk 2 t rsc 20 ns 20 mode register set cycle time t t 130 ns 130 transition time t ref 16 ms 16 refresh time max. t pde 8ns 10 cke setup time (precharge power down exit)
34/66 ? semiconductor msm54v25632a timing waveform ac parameters for read timing (bl = 2, cl = 2) clk 0 cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq ? ? y {| ~ ? hi-z t ckh t cms t cmh t ck t ch t cks t cms t cmh t cl z { ? ? z { } ~ } ~ ? ? ? ? z { ? ? z { } ~ ? z ? z } } ? ? z ? z } y y y | | y | | } ? ? { ? { ? { ~ ? { ~ ~ ? z { ? ? z { } ~ ? ? ? ? z { } ~ ? ? y z ? y z | } ? z z } } ? ? | | | y y t as t ah dsf ? y { ? y {| ~ | ~ ? ? y { ? y {| ~ t rc t ras t rrd t rp t rcd t lz t oh t oh t ac t ac t hz 12345678910111213 auto precharge start for bank b act-a rd-a act-b rap-b pre-a act-a
35/66 ? semiconductor msm54v25632a ac parameters for write timing (bl = 4, cl = 2) clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq hi-z 0 dsf t cms t cmh t as t ah t cms t cmh t ds t dh t rcd t rrd t dal t dpl t rp t rc t ckh ? y {| ~ | ~ | ~ ? z { ? ? ? ? z ? } } ? } z } z } ? y y { ? | | | y | y | } ? ? ? ? y { ? | ~ ? | ~ ? z { ? ? z { } ~ ? ? { { ~ ~ ? ? ? y { | ~ ? | ~ y { ? ? ? { ~ ~ ~ ? { ~ ? ~ { ? ? ? ? z { } ~ } ~ ? ? z { } ~ ? ? } ~ ? ? } ~ y {| ~ 123456789 21 20 19 18 17 16 15 14 13 12 11 10 t cks auto precharge start for bank b auto precharge start for bank a act-a act-b wap-a act-a wap-b wap-a pre-a act-a
36/66 ? semiconductor msm54v25632a relationship between frequency and latency rate 36 msm54v25632a-12 18 12 30 msm54v25632a-10 15 10 clock cycle time [ns] 28 55 83 33 66 100 frequency [mhz] 1 2 3 1 2 3 cas latency 1 2 3 1 2 3 [t rcd ] 2 4 6 2 4 6 ras latency ( cas latency + [t rcd ]) 3 6 9 3 6 9 [t rc ] 2 4 6 2 4 6 [t ras ] 1 2 2 1 2 2 [t rrd ] 1 2 3 1 2 3 [t rp ] 1 2 2 1 2 2 [t dpl ] 2 3 5 2 3 5 [t dal ]
37/66 ? semiconductor msm54v25632a power on sequence and auto refresh (initialization) 02356891011131517182021 clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq dsf pre (all banks) ref ref hi-z t rc t rc mra { { ~ ~ ? ? z z } } ? ? { ~ ? ? z { } ~ ? ? ? ? z { ? ? z { } ~ } ~ ? ? ? y {| ~ ? ? y { ? y {| ~ | ~ ? z z { { } ~ ? ? ? ? ? z } ? ? z ? z } } ? } ~ ? ? y | y y | | z { } ~ } 1 4 7 12 14 16 19 address key high level is necessary 8 refresh cycles are necessary high level is necessary
38/66 ? semiconductor msm54v25632a mode register set (bl = 4, cl = 2) clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 2 3 4 5 6 9 1112 1415 1718 2021 dsf pre (all banks) mra act t rp hi-z h z } } ? ? | { { ~ ~ ? ? y | | y | y z | } | } y z | | } } ? ? y | y z z { } ~ } ~ z { } } ~ ~ ? ? ? ? z { } z } y z | | } } ? ? | } y y | | y z | } y z | { ~ ~ { ~ ~ ? ? { 1 7810131619 t rsc (20 ns) address key
39/66 ? semiconductor msm54v25632a auto refresh (cl = 2) clk cke h cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 dsf pre ref ref act rd t rp t rc t rc z z } ? z } ? z ? ? | } y | { ~ { ~ ? { ~ ? { ? y | | ~ ? ? y y z ? y {| ~ ? y {| ~ ? y { y { ? } ~ z z { { } } ~ ~ ? ? ? ? z { ? ? } z z } } ? ? | } ? y y z z | | } } ? ? l 1 2 3 4 5 6 7 8 9 101112131415161718192021 q1
40/66 ? semiconductor msm54v25632a self refresh (entry and exit) clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq dsf pre sref entry sref exit sref entry or (act) sref exit next clock enable next clock enable act t rp t rc t rc 0123 7891011 1718192021 412 l y ? z } ? z } ? } ? y z | } y z | } ? ? y {| ~ z } y {| ~ ? y { | ~ ? | ~ ? y z | } ? y | ? | } ? } ? y | y | { ? { ~ ? | { { ~ ? ? { ~ ~ ? z z } ? ? z } z } z z } } ? ?
41/66 ? semiconductor msm54v25632a auto precharge after read burst (bl = 4, cl = 3) clk cke h cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 dsf act-a act-b rd-a rap-b act-b rap-a l hi-z ap-b ap-a rap-b y {| ~ z { } ~ z } z } | ~ ? z } z } ? z { ? ? z { ? ? y { ? y y | | | } ? z } ? | ~ { ~ ~ ? y {| ~ { ~ { ? y { { | ~ ? ~ ? } ~ ? ? ~ } z ? z } } ~ ? ? } ~ z { } ~ z ? } ? y | | y | | y y | 123456789101112131415161718192021 qbb2 qbb1 qab4 qab3 qab2 qab1 qba4 qba3 qba2 qba1 qaa4 qaa3 qaa2 qaa1 cbb rbb caa cba rba cab raa raa rbb rba
42/66 ? semiconductor msm54v25632a auto precharge after write burst (bl = 4, cl = 3) clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq dsf h 0 act-a act-b wt-a wap-b wap-a wap-b l hi-z ap-b act-b ap-a | | | ~ ? | y | y | y | { { ~ ~ ? ? ? y { ? y {| ~ y { ? } ? z ? } ? z } z } z ? y ? ? y {| ~ | ~ ? y | y | y ~ ? { ? { ~ { ? ? { ~ ~ ? } ~ ? ? z { ? ? z { } ~ z { ? ? ? ? z { } ~ } ~ ? ? 123456789101112131415161718192021 dbb4 dbb3 dbb2 dbb1 dab4 dab3 dab2 dab1 dba4 dba3 dba2 dba1 daa4 daa3 daa2 daa1 cbb rbb caa cba rba cab raa raa rbb rba
43/66 ? semiconductor msm54v25632a full page read cycle (cl = 3) clk cke h cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 dsf act-a rd-a act-b rd-b burst cannot end in full page mode pre-b act-b l hi-z burst stop command t rp y y y } z } y z | } ? ? z ? z } z z ? | y | y | y z ? y z ? y z | } y y y { { { | | ~ ~ ? ? y z y y y | | y { y { ? y { ? ? | ~ | } ? y {| ~ y {| ~ { ~ { { ? { ~ { ? ~ 123456789101112131415161718192021 qba+3 qba+4 qba+5 qba+2 qba+1 qba qaa+1 qaa qaae1 qaae2 qaa+1 qaa rbb rba cba rba rbb qaae3 caa raa raa
44/66 ? semiconductor msm54v25632a full page write cycle (cl = 3) clk cke h cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 1 dsf act-a wt-a act-b burst cannot end in full page mode wt-b pre-b act-b l hi-z burst stop command t rp ? ? } ~ ? ? z { } ~ y { y { ? { ? y {| ~ { ~ z { } ~ y {| ~ y { ? ? | ~ ? z { z { ? ? z { ? ? ~ ? { ~ { ? z z } } ? ? ? ? z { } ~ ? ? z z { { } ~ ? ? ? ? ? } ? z } z } z { y | z ? z ? y y y | y | 03 25 47 69 811 10 13 12 15 14 17 16 19 18 21 20 rbb rbb cba caa raa raa rba rba dba+3 dba+4 dba+2 dba+1 dba daa+1 daa daae1 daa+3 daa+2 daa+1 daa
45/66 ? semiconductor msm54v25632a pre (precharge) termination of burst (bl = 2, 4, 8, full, cl = 3) clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 01 dsf dqm 0 - 3 act-a wt-a rd-a act-a pre-a pre command termination l hi-z h pre-a act-a pre command termination t dpl t rp t rp t ras t rcd { { ~ ~ ~ ? ? y z ? y z ? ? | } ? y z ? y z | } y z | } | } | y y | y | | { ~ { ? ~ { ? ? ~ z } ~ ? { ~ z { } ~ z { ? ? } ~ z { ? ? ? ? } ~ } ~ ? ? z { } ~ z } } } ? } ? z ? ~ { ~ ? { ~ ? { ? } ? 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 qab3 qab2 qab1 daa1 rac caa rab cab raa raa rab rac daa2
46/66 ? semiconductor msm54v25632a clock suspension during burst read (using cke function) (bl = 4, cl = 3) clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 dsf dqm 0 - 3 act-a rd-a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at end of burst l } z z } } ? ? | } y y z z | | } } ? ? | y y | | ~ { { ~ ~ ? ? z z } } ? ? | } ? } ? } | } y y z z | | } } ? ? } ? | } ? ~ ? ~ { { ~ ~ ? ? ~ ? | 1 2 3 4 5 6 7 8 9 101112131415161718192021 qaa2 qaa3 qaa4 caa raa raa qaa1
47/66 ? semiconductor msm54v25632a clock suspension during burst write (using cke function) (bl = 4, cl = 3) ? ? z z { { } } ~ ~ ? ? ? ? ? z z } } ? ? y y | | z z { { } } ~ ~ ? ? ? ? z z { ? ? ? z z } } ? ? z { z ? y y z z | | } } ? ? y z y ? { { ~ ~ ? ? { y | | | clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 dsf dqm 0 - 3 l caa raa raa act-a 1-clock suspended 2-clock suspended 3-clock suspended wt-a daa4 daa3 daa2 daa1 123456789101112131415161718192021
48/66 ? semiconductor msm54v25632a power down mode and clock suspension (bl = 4, cl = 2) clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 dsf dqm 0 - 3 l valid act-a rd-a active standby precharge standby pre-a pd pd entry pd exit clock mask start clock mask end pd t cks t pde y { | ~ ? z { ~ y {| ~ y { { { ~ ~ ? ? y {| ~ | y { | | ~ ~ ? } ~ ? ? } ? z { } } ~ ~ ? ? { ~ ? { ~ { ~ ~ ? z } z } } ? y | y | y | | | ~ ? y { | | ~ ~ ? z { z { } ~ y | y 123456789101112131415161718192021 caa raa raa qaa4 qaa3 qaa2 qaa1
49/66 ? semiconductor msm54v25632a clock suspend exit & power down exit clk 2) power down (= precharge power down) exit (case 1) cke internal clk command (case 2) cke internal clk command note 2 act nop act 3 t pde note 2 < t pde note 3 note 4 clk 1) clock suspend (= active power down) exit cke internal clk command note 1 rd t cks notes: 1. active power down: one or both bank active state. 2. precharge power down: both bank precharge state. 3. t pde : asynchronous ac parameter. time for power down exit setup time. only valid at precharge power down exit. 4. t cks < t pde , nop should be issued. and new command can be issued after 1 clock.
50/66 ? semiconductor msm54v25632a byte read/write operation (by dqm) (bl = 4, cl = 2) clk cke cs ras cas we a9 (ba) a8 add dqm dqm1 0 dsf dqm0 h act-b rd-b byte of dq8 - 15 not read byte of dq0 - 7 not read byte of dq0 - 7 not write wt-b byte of dq8 - 15 not write byte of dq0 - 7 not read byte of dq0 - 7 not read byte of dq0 - 7 not write dq 0 - 7 dq 8 - 15 ? ? y { z { ? ? z } ? y {| ~ ? } ~ ? ? z { } ~ ? ? z z { z } ? z ? y {| ~ ? y { ? } ~ ? ? ? { { ~ ? { ~ ? { ? ? ? z { } ~ ? ? y | y y | y y { ? z { ? ? } ? } ? z ? y {| ~ ? y {| ~ ? y { ? { { ~ ~ ? ? 1 2 3 4 5 6 7 8 9 101112131415161718192021 qba4 qba3 qba2 dbb2 dbb1 dbb4 qbc2 qbc1 qbc3 qbc4 qba1 qba3 qba2 dbb2 dbb3 qbc2 qbc3 rba rba cba cbb cbc rd-b
51/66 ? semiconductor msm54v25632a burst read and single write (bl = 4, cl = 2) clk cke cs ras cas we a9 (ba) a8 add dqm1 dq 0 - 7 dq 8 - 15 0 dsf dqm0 act-b rd-b single wt single wt rd single wt h write masking z z } } ? ? ? y ? ? z ? y ? { ? z } y | { ~ z } ? y | } ? | z } { ~ ? { ? z ? y ? ? ? y z | } y z | } ? z ? y z ? { ? } ? | } ? | ~ ? } ? y | | y z ? ? y { ? ? { ? ? y { ? { ~ y {| ~ { ~ ? y {| ~ ? ~ ? | ~ ? 123456789101112131415161718192021 qba1 qba2 qba3 qba4 dbb dbc cbb cbc cbd cbe dbe qbd1 cba rba rba
52/66 ? semiconductor msm54v25632a special mode register set (bl = 4, cl = 2) z ? y { ? z } ? | ~ ? ~ ? z { } ~ ? ? | } ? y z ? { y y { { ? z z } } ? { { ~ ~ ? y y | | y y { { | | ~ ~ ? z { z z { { } } ~ ~ ? ? z z z } } ? y z y y z z | | } } ? y z | } ? y y | | y | clk cke cs ras cas we a9 (ba) a8 add dqm 0 - 3 dq 0 dsf smra pre (all banks) remark special register set command can be input at any state. act is valid h hi-z t rp 1 2 3 4 5 6 7 8 9 101112131415161718192021 t rsc (20 ns) address key color or mask data
53/66 ? semiconductor msm54v25632a random row write with wpb (bl = 8, cl = 3) y {| ~ { ~ z } ~ ? { } ~ ~ ? } ~ ? ? y { ? { ? z ? } z z { y y { z ? } ? z } z { } ~ } z | | ~ y y { ? ? | | ~ ? } ~ ? ? | ~ ? y | y z { ? ? z y { { z z { | y z { } ? } z ? z y { ~ y | | y y | } clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a with wpb wt-a wpb is enabled. act-b wt-b wpb is disabled. wt-a wpb is disabled. pre-a pre-b act-a h l t rcd t dpl t rp t dpl daa1 daa2 daa3 daa4 daa5 daa6 daa7 daa8 dba1 dba2 dba3 dba4 dba5 dba6 dba7 dba8 dab1 dab2 dab3 raa raa caa rba rba cba rab rab cab 123456789101112131415161718192021
54/66 ? semiconductor msm54v25632a block write (page at same bank) (cl = 3) clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-b bw-b bw-b bw-b bw-b bw-b wpb is enabled. pre-b act-b with wpb h t rcd t rcd t rp t bpl t bwc t bwc z z } } z { ? ? } ~ ? ? | ~ ? } ? z { ? ? y { ? y y { ? } ? z { } ~ } ~ ? ? | ~ ? z ? z } y | } } ~ | z { z { } ~ } ~ y { { ? ~ ? { ? y {| ~ { ~ y {| ~ | ~ { { ~ ~ z ? } ~ | ~ ~ z { ? ? z { ? ? z { } ~ } ~ ? ? } } ? y | z ? z z } } z } z } ? y y | | y | | | y y | | | z { z { } ~ } ~ } ~ ? ? | ~ ? y 12345678910111213141516171819 rba rba cba cm cbb cbc cbd cm cm cm cm i/o mask i/o mask i/o mask i/o mask l = no i/o mask rbb cbc rbb i/o mask t bwc
55/66 ? semiconductor msm54v25632a block write (page at same bank) changing color and mask data (cl = 3) ? { ? { { ~ ~ y { ? z ? y {| ~ { ~ | ~ ? y { ? y {| ~ z { ? ? ~ ? ? ~ ? ? ? z { ? ? z { z { } ~ } ~ } ~ ? ? y y y | | | z { } ~ z } } ~ ? ? y { | ~ ? } ? y { z } ? y | | ? z ? z z } } | ~ y y | y | | { ? y { z { y y | y { z } y | { ~ ~ ? { ? { { ~ ~ { ~ ? ? z ? z z } } z } ? clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-b with wpb bw-b smra (mask data) bw-b smra (color data) pre-b act-b bw-b bw-b h t rcd t bpl t bwc t rsc (20 ns) t bwc t rsc (20 ns) t bwc t rcd cm rba rba cba 20h cbb 40h cbc cbd rbb rbb mask cm color cm cm i/o mask i/o mask i/o mask i/o mask 12345678910111213141516171819
56/66 ? semiconductor msm54v25632a interleaved block write (cl = 3) clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a bw-a bw-b bw-b bw-a act-b pre-b h l t rp t bpl t bwc t bwc t rcd t rcd column mask z { | z { } ~ ? { ~ z { } ~ ~ ? y | ? } ~ ~ } ~ ? ? y z z } } { { ~ ~ z } } ? { ? { { ~ ? ? z { ? ? z ? y ? ~ ? { ? { ? y z | } { { ~ ? { { ~ ~ ? ? y z y z | } y z | } ? ? y z | } y | | } ? | } y z ? y z | y z | } 12345678910111213141516171819 act-b cm raa raa caa rba cba cab cbb rba cm cm cm rbb rbb
57/66 ? semiconductor msm54v25632a random column read (page with same bank) (bl = 4, cl = 3) { { ~ ~ ? ? ? ~ } z ? ? z ? z } } ? y {| ~ y { ? z ? { ? z { ? ? z { } ~ { ? y { | ~ ? { ~ ? y { ? z { ? ? ? ? { ~ z { | ~ } ~ ? ? ? } ~ ? ? ? ? ? y {| ~ y { | ~ ? y { ? | y y | ~ y { ? ? y | | y ? clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a rd-a rd-a pre-a act-a rd-a rd-a h l t rp raa raa caa cab cac raa caa raa qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 123456789101112131415161718192021
58/66 ? semiconductor msm54v25632a random column write (page with same bank) (bl = 4, cl = 3) clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-b wt-b wt-b wt-b wt-b act-b pre-b h l t rp dbb2 dbc1 dbc2 dbc3 dbc4 dbd1 dba2 dba1 dba3 dba4 dbb1 123456789101112131415161718192021 ? z } } ? z ? z } z ? z z y | { ? { ~ ~ ? { ? { ? { ~ { y z ? y z y z | } y z | } | } ? y z ? y z ? y y y z z z | | } } ? ? rba cba cbb cbc rbd cbd ? } ? z ? z } z ? z } z z rba rbd z { ? ? z { } ~ } ~ ? ? z { ? ? z { ? ? z { } ~ z { y y | y y y |
59/66 ? semiconductor msm54v25632a random row read (bl = 8, cl = 3) y y z z | | | } } } ? ? ~ ? { ~ z { } ~ ? { ? ~ ? } ? z } { ~ { ? ? } ~ | } } ~ | } ~ ? ? y z ? | } ? y z | } } ? z } z ? z { } ~ | y | | } ? y z | } y z ? z ? z { ? ? } ? z } } | ~ } ~ } | } ~ ? ? ? ? z { ? ? y | y y ? | } z ? ? } ? z } z } clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-b act-b act-a rd-b rd-b rd-a pre-b pre-a h l t rp t rcd cl rba rba raa rbb cba raa caa rbb cbb qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 qba2 qba1 qba3 qba4 qba5 qba6 qba7 qba8 qaa8 123456789101112131415161718192021
60/66 ? semiconductor msm54v25632a random row write (bl = 8, cl = 3) | } ? | } ? y z y y z ? } ? | } ? ~ ? z } ? ~ | } | | } ~ } z { ? ? } ~ ? ? z { } ~ ~ ? { ~ { } ~ ? ? } ~ z ? y ? } ? } z { z { ? ~ ? | { ~ ~ } y z | } { ~ | } ~ y | ? ? } ~ y | | ? { ? ~ ? ~ { ~ ~ ? ~ ? { { ? ~ ~ { ~ clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a act-a pre-a pre-b wt-a wt-b wt-a h l t dpl t rcd t rp t dpl dba1 dba2 dba3 dba4 dba5 dba6 dba7 dba8 dab1 dab2 dab3 daa2 daa1 raa cba rab rab cab daa3 daa4 daa5 daa7 daa8 raa caa 1 2 3 4 5 6 7 8 9 101112131415161718192021 act-b rba rba daa6
61/66 ? semiconductor msm54v25632a read and write (bl = 4, cl = 3) { ~ z { } ~ y | { ~ ? y | { ~ z { y y z } y | y | y | | ~ ? y | z } ? z } } ? | y z | } y z | } y z | } ? z } y z z | } ? z { } ~ ? ? z } ? z { } ~ z { } ~ ? ? z } } ? clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a rd-a wt-a rd-a hi-z at the end of burst function 0-clock latency 2-clock latenc y hi-z h raa caa cab cac dab1 dab2 dab4 qac1 qac2 qaa1 raa qaa2 qaa3 qaa4 123456789101112131415161718192021 write latency = 0 write masking
62/66 ? semiconductor msm54v25632a interleaved column read cycle (bl = 4, cl = 3) { { ~ ~ ? ? ? { ? { } ? ? z } y | z ? z } | ~ ? y { z y { z | ~ ? ~ y {| ~ | | ~ } ~ ? { ~ y | ? ? y { ? y { } ? } ? ? ? ? y { ? y { | ~ | ~ ? ? ? } ? z } z ? | y z ~ ? ? y {| ~ y { | ~ ? clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a rd-a rd-b rd-b rd-b rd-a pre-b pre-a act-b h l t rcd t rrd cl raa caa rba cba cbb cbc cab raa qbc1 qbc2 qab1 qab2 qab3 qab4 qaa2 qaa1 qaa3 qaa4 qba1 qba2 qbb1 qbb2 rba 123456789101112131415161718192021
63/66 ? semiconductor msm54v25632a interleaved column write cycle (bl = 4, cl = 3) z z } } } ? ? } } ? ? | | y { | ~ ? ? | ~ ? ? z { } ~ } ~ ? ? | ~ ? ~ ? } ? | z { { ~ ? ? ? z y ? ? } ~ } ~ } ~ ? ? ? ? y | y {| ~ | | ~ } ~ } ~ ? ? ? ? z { } ~ } ~ ~ { ~ z } } ~ ? ? } ~ ? ? z { clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a wt-a wt-b wt-b wt-b wt-a wt-b pre-b act-b pre-a h l t rcd t rrd t dpl t dpl raa caa rba cba cbb cbc cab cbd raa dbc1 dbc2 dab1 dab2 dbd1 dbd2 dbd3 dbd4 daa2 daa1 daa3 daa4 dba1 dba2 dbb1 dbb2 rba 123456789101112131415161718192021
64/66 ? semiconductor msm54v25632a full page random column read (bl = full page, cl = 2) y y | | | y ? ? y | | { { ~ ~ ? | } ~ } | ~ ? z } ? z } y z | } ? y z y z | } | } ? { { ~ ~ { ~ ? { ~ ? y z y z | } | } ? y z | } ? ? ? y | z } ? ? | } clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a act-b rd-b rd-a rd-a rd-a rd-b rd-b pre-b ( pre termination ) h l t rcd t rrd t rcd raa rba caa cba cab cbb cac cbc qac3 qbc1 qbc2 qbc3 hi-z qba1 qaa1 qab1 qab2 qbb1 qbb2 qac1 qac2 rba raa 123456789101112131415161718192021
65/66 ? semiconductor msm54v25632a full page random column write (bl = full page, cl = 2) z z } } ? ? y z ? } | ~ y z y z | } y { ? y { y {| ~ | ~ ? } | ~ ~ | } | | } ? ~ { ? { ~ } ? { z ? z ? z z } | y y { ? z ? z z } } ? z ? | } | ~ ? y z ? { ? } } y y y | ? clk cke cs ras cas we a9 (ba) a8 add dq 0 dsf dqm 0 - 3 act-a act-b wt-b wt-b wt-b pre-b (pre termination) wt-a wt-a wt-a h l t rcd t rrd t rcd raa rba caa cba cab cbb cac cbc dac3 dbc1 dbc2 dbc3 dba1 daa1 dab1 dab2 dbb1 dbb2 dac1 dac2 rba raa 123456789101112131415161718192021
66/66 ? semiconductor msm54v25632a (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp100-p-1420-0.65-bk4 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.54 typ. mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-11

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